Non-volatile memories are those memories that are capable of retaining the data stored in their cells for a significantly long time, usually in excess of ten years, after they were disconnected from a power supply. The use of floating gates in non-volatile memory, and in particular in metal-oxide semiconductor field effect transistors (MOSFET) is common in the art Digital devices include Electrically Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), and Flash memories. Digital devices typically have a range of a data or other information corresponding generally to a logic value of “0” or a logic value of “1”. These devices have a large range of uses in both embedded and stand-alone applications. However, requirements from such memory may vary significantly depending on the specific application in which such memory is to be used. For example, in some cases, the dominant requirement is for the storage of large quantities of data that may require emphasis on the smallest possible cell size. In other cases, the amount of data to be stored is quite small and it is important to ensure that the additional costs that are required for enabling a circuit to be a non-volatile memory are minimized.
An industry requirement for non-volatile memory cells is retention of data stored in a non-volatile memory cell. Retention is the ability to retain the data stored in the cell for an extended period of time after the cell was disconnected from its power source. The typical industry standard for retention is ten years. Charges can be trapped in a memory cell to represent information, such as a logical “1” or a logical “0.” Charges can leak out of a memory cell diminishing the ability to sense the logic state of the cell. The loss of charges trapped in a non-volatile memory cell can occur while the device is connected to its power supply. In fact, charge loss may be enhanced during chip operation due to its relatively higher operating temperature that results in a high level of charge-loss. If a memory cell looses enough of its stored charge, it may be impossible or at least impractical to attempt to sense the low residual charge voltage remaining in the cell.
Attempts to address the problem of charge loss take a multitude of ways especially in cases where the charge loss is significantly fast. A common approach to address the problem is through process solutions that provide better ways of trapping charges and keeping them in place. One such attempt can be found in U.S. Pat. Nos. 5,801,076, 5,805,013, by Ghneim et al., where the floating gate can be configured as a stacked or non-stacked pair of polysilicon conductors. Li et al. suggest in U.S. Pat. Nos. 5,854,114 and 6,064,105 a shallow trench isolation (STI) approach designed to maintain sufficient retention in a non-volatile memory cell. Maiti ct al. take the approach of providing a better oxidation to the layers in U.S. Pat. No. 5,885,870 and thereby enhancing the retention of the floating gate device. Increased retention by substantially overlapping or encapsulating the floating gate by the control gate, therefore keeping the gate isolated from other structures, such as sidewall spacers, is another way of addressing the issue and is suggested by Rahim in U.S. Pat. No. 6,069,382. However, all these approaches suggest changes to a process to achieve the goal of better retention. This may prove costly due to the effects on other portions of the design and the departure from a standard and known process flow.
Another approach is to try and correct the charge-loss problem by using circuit solutions. In some cases, this approach may increase the physical size of the non-volatile memory containing all the cells. In U.S. Pat. No. 5,251,171, Yamauchi suggests a circuit to achieve the goal of higher retention of a non-volatile memory cell. The circuit couples the non-volatile cell and a capacitor capable of storing charges. This capacitor is charged periodically, similar to the refresh process in a dynamic random access memory (DRAM). By applying the capacitor to the non-volatile memory cell its charge loss is reduced. Another approach to refresh, suitable also for multilevel applications, is suggested by Wang in U.S. Pat. No. 6,018,477. Using a sensing device and a comparator a trigger is generated to cause a refresh of the cell upon charge-loss potentially causing the change in the content of the non-volatile memory cell. As a result of the trigger, the cell is reprogrammed to ensure proper operation. A problem with the refresh approach is that due to a rapid charge loss of the DRAM capacitor relatively frequent refreshes can be necessary. The frequent refreshes occur due to the relatively small capacitor size that can be integrated in such a cell, and because the discharge time is directly proportionate to the value of the capacitor, which is small to begin with. In applications that are power consumption sensitive, the frequent refreshing may deprive a significant number of use hours from the user.
FIG. 1 illustrates a graph showing typical loss of charge in a non-volatile memory cell over time. The graph illustrates an initial charge 105 stored by the non-volatile memory cell. The charge 110 stored by the non-volatile memory cell decreases over time. After programming, the discharge of a non-volatile memory cell discharge begins moving towards a residual value. A sufficient margin 120 should exist between the maximum sensing error and the stored charge to read the data stored by the cell and receive valid results. However, over time the charge loss becomes significant and falls below a sensing threshold voltage, indicated by line 120. Below the sensing threshold voltage 120 it may be impossible to distinguish between the programmed and erased values of the cell, resulting in an erroneous readout.
Also, the loss of charge 110 stored in the non-volatile memory cell may be accelerated by higher than normal operating temperatures. The accelerated charge loss can result in an overall retention being significantly below an industry standard for non-volatile memory cells.